1. Field of the Invention:
The present invention relates to a phase-locked loop (PLL) apparatus for use with synthesizer tuners containing a pre-scaler arrangement and, more particularly, to a digital type phase comparator which, together with a charge pump circuit and a low-pass filter, constitutes a phase-locked loop system.
2. Description of the Prior Art:
FIG. 1 shows a partial construction of a prior art PLL synthesizer tuner for use with a television set. In the construction of FIG. 1, an RF signal RF1 generated by a local oscillator 1 is supplied via an amplifier 2 to a pre-scaler 3 which is a fixed divider. The pre-scaler 3 divides the RF signal RF 1 by 4. The divided output is sent via the output terminal of the pre-scaler 3 to a phase-locked loop apparatus 4.
There may be assumed a case in which the tuner of the above construction is used to receive, say, channel 4 on the Japanese television frequency VHF band. In that case, the local oscillation frequency is 230 MHz. Dividing that local oscillation frequency by 4 equals 57.5 MHz. This is where one disadvantage of the prior art develops. That is, the signal of the above divided frequency tends to intrude into the intermediate frequency band of 58.75 MHz, causing a beat.
One solution to the unwanted generation of the beat is a method disclosed in Japanese Patent Laid-open No. 57-84629. This method involves equipping the substrate of the apparatus with means to lower the leakage of the signal of the divided frequency.
However, the disclosed method has failed to address drastically the problem of the beat. The need is left unfulfilled for a synthesizer tuner with a phase-locked loop apparatus that would prevent leakage of the signal of the divided frequency into the intermediate frequency band.
There is known a PLL digital type phase comparator that compares a reference pulse signal E (called the E signal) with a compare pulse signal F (called the F signal), the E and the F signals being supplied by a reference signal oscillator and a voltage-controlled oscillator, respectively. Though the compare operation, the phase comparator generates an UP signal or a DOWN signal and varies it in terms of level.
FIG. 2 depicts the construction of one such prior art digital type phase comparator. This phase comparator comprises six two-input NAND circuits 11 through 16 and three three-input NAND circuits 17 through 19. The E signal given to a first input terminal G.sub.1 is forwarded to a first two-input NAND circuit 11. The F signal given to a second input terminal G.sub.2 is sent to a sixth two-input NAND circuit 16. The output of the first two-input NAND circuit 11 is fed to a first and a third three-input NAND circuit 17 and 19 as well as to a second two-input NAND circuit 12. Meanwhile, the output of the sixth two-input NAND circuit 16 is supplied to the second and third three-input NAND circuits 18 and 19 as well as to a fifth two-input NAND circuit 15.
The output of the second two-input NAND circuit 12 is given to the first and third three-input NAND circuits 17 and 19. The second two-input NAND circuit 12 and the third two-input NAND circuit 13 feed back their outputs to each other. Likewise, the fifth two-input NAND circuit 15 and a fourth two-input NAND circuit 14 feed back their outputs to each other. Furthermore, the output of the third three-input NAND circuit 19 is fed to the first and second three-input NAND circuits 17 and 18 as well as to the third and fourth two-input NAND circuits 13 and 14.
The output of the first three-input NAND circuit 17 is output as an UP signal to a first output terminal G.sub.3 and fed back to the first two-input NAND circuit 11. The output of the second three-input NAND circuit 18 is output as a DOWN signal to a second output terminal G.sub.4 and fed back to the sixth two-input NAND circuit 16.
As described, the typical prior art phase comparator requires as many as nine NAND circuits: six two-input NAND circuits 11 through 16 and three three-input NAND circuits 17 through 19. In addition, the output of each NAND circuit is fed back to other NAND circuits in a complicated feedback scheme so that the level of the UP signal and that of the DOWN signal are varied in accordance with the phase status of the input E and F signals. Thus the prior art phase comparator has a large circuit arrangement that fails sufficiently to meet the need for a smaller comparator size. The complex wiring involved calls for more steps of manufacture, making it difficult to reduce production cost.